1. Field of the Invention
The present invention relates to a program control system which executes plural processes by switching according to the status.
2. Discussion of the Related Art
Conventionally, a CPU has executed process switching according to the status (or, referred to as Context Switch) by interrupt or branch instruction. FIG. 7 is a schematic view showing an ordinary CPU system. In the figure, a CPU is indicated by 41, a memory is indicated by 42, an address bus is indicated by 43, a data bus is indicated by 44, a data bus buffer is indicated by 51, an internal data bus is indicated by 52, a control signal I/O interface is indicated by 53, an instruction register is indicated by 54, an operation part (or arithmetic and logic unit, hereinafter referred to as ALU) is indicated by 55, a program status word (hereinafter, referred to as PSW) is indicated by 56, a register is indicated by 57, an instruction decoder is indicated by 58, a controller is indicated by 59, a program counter (PC) is indicated by 60, an address bus buffer is indicated by 61 and an internal address bus is indicated by 62.
The CPU 41 reads one of programs stored in the memory 42 and operates in accordance with the read content. The counter 60 specifies a position of storing the program, namely, an address. The CPU 41 outputs a value of the program counter 60 to the address bus 43 through the internal address bus 62 and the address buffer 61, for reading the contents of the memory 42. The contents, namely, the instructions are provided to the instruction register 54 through the data bus 44, the data bus buffer 51 and the internal data bus 52. A cycle of reading an instruction to be executed, as described above, is called a fetch cycle.
The instruction provided to the instruction register 54 by the fetch cycle is interpreted by the instruction decoder 58 to execute operation in accordance with the instruction, reading or writing the data from/to the memory, transfer to the I/O interface 53 or the like through the controller 59. At this time, carrying out of the operation is executed by the ALU 55, and operand or the result of operation is stacked in the register 57. Moreover, a flag indicating the status of the result of operation is stacked in the PSW 56. FIG. 8 illustrates an example of the PSW, which shows four flags. The flag N is set to 1 when the result of the operation is negative, otherwise it is set to 0. The flag Z is set to 1 when the result of operation is 0, and when the result of operation is other than 0, it is set to 0. The flag V is set to 1 when the operation causes overflow, and set to 0 when the operation causes no overflow. The flag C is set to 1 when the carry is generated in the operation, otherwise set to 0. There is, of course, a case where other flags are set in the PSW 56. A cycle executing various processes in accordance with the instruction read by the fetch cycle, as described above, is called an execution cycle. A register held inside of the CPU 41 frequently used for stacking data, such as the register 57 or the PSW 56, is called a system register. The CPU 41 basically repeats the fetch cycle and the execution cycle alternately.
Only if an external request of execution of other process is made, that is, an interrupt is made, the system proceeds to an interrupt processing cycle after the execution cycle. In FIG. 7, the interrupt is input through the control signal I/O interface 53. FIG. 9 is a flow chart showing a procedure of an ordinary interrupt process. In the figure, it is assumed that a process prior to the interrupt is process #1 and a process executed by the interrupt is process #2. In process #1, which is prior to the interrupt, the instruction fetch cycle in step 71 and the instruction execution cycle in step 72 are alternately repeated as described above. When the interrupt occurs, it is detected in step 73 and the system moves to the interrupt processing cycle.
In the interrupt processing cycle, values of the PSW 56 and the program counter 60 are first stacked in steps 74 and 75, and then the contents of the program counter 60 is changed in step 76. The address to be changed is determined in accordance with the type of the interrupt signal. At the branching destination address of the interrupt process, an interrupt processing program is located. In process #2, which is the interrupt processing program, the instruction fetch cycle in step 77 and the instruction execution cycle in step 78 are alternately repeated as same as process #1. At the end of the interrupt processing program, the system proceeds to steps 79 and 80, and further in steps 80 and 81, the values of the PSW 56 and the program counter 60 are restored to the former values, whereby the process returns to process #1 at the time when the interrupt occurs. This kind of ordinary interrupt operation is described in various references, such as "Transistor Technology", CQ publishing company, Vol. 6, 1991, pp. 456-458.
Other than the interrupt process, it is also possible to switch to the other process which is under execution. In this case, a branch instruction is used. FIG. 10 is a flow chart showing a procedure of processing an ordinary branch instruction and is indicating a case where process #1 branches into process #2. As described above, the instruction fetch cycle and the instruction execution cycle are alternately repeated in process #1. Steps 91 and 92 indicate fetch and execution, respectively, on the instruction prior to the branch instruction. If the process is changed by the branch instruction, a processing result or change of the external status, which is the condition of changing, is reflected in the PSW 56. The CPU 41 fetches the branch instruction in step 93, reads the status stored in the PSW 56 in step 94, and determines whether the status satisfies the branch condition in step 95. If the status does not satisfy the branch condition, fetch and execution of next instruction in process #1 are continued without branching as shown in steps 96 and 97. If the read status satisfies the branch condition, the value of the program counter 60 is changed to the specified address in step 98 to switch the process. Then, as shown in steps 99 and 100, fetch and execution of the instruction in process #2 are alternately repeated. The procedure of processing of such branch instruction is also described in various references, such as, the above-described "Transistor Technology"CQ publishing company, Vol. 6, 1991, pp. 448-449.
If it is required that the plural processes are executed by switching appropriately in accordance with the process result, change of the external status or external request with high-speed or in real time, there occur the following problems in process switching by interrupt or branch instruction in the CPU.
In the case of interrupt, processes of stacking in the PSW and the program counter, and changing of the program counter are carried out within the period of switching from one process to another (long interrupt). These processes cause overhead which cannot be ignored if quick operation for process switching is required. For example, as noted in "M68000 Microprocessor User's Manual", Motorola Inc., CQ Publishing Company, Appendix D, page 189, MC68000 requires 44 clocks during the period from accepting the interrupt to fetching the first instruction of the interrupt processing routine. In the case of the process which does not require stacking in the register such as the PSW (short interrupt), it is possible to reduce or delete the stacking operation, but the process of changing the program counter is still necessary, and is left as the overhead in process switching.
In the case of process switching according to the branch instruction, execution of the branch instruction itself, that is, reading the PSW, condition determination and changing the program counter, is necessary, and results in the overhead which cannot be ignored as same as the case of the interrupt process. In the case of MC68000 described above, 8 clocks or more are required even in the case of jump instruction without condition determination. The branch instructions must be located on the points having potentiality of occurrence of process changing in the program.
As described above, if the process switching is carried out by interrupt or branch instruction in the CPU, the overhead necessarily occurs in switching. The delay in processing caused by the overhead comes into problem if the process is desired to be executed at high-speed or in real time.
FIG. 6 illustrates an example of a process flow. The problem described above is now illustrated by taking the process flow shown in FIG. 6 as an example. In the process flow, the system repeats process 0 as a normal procedure. If request S is made, the system moves to process 1. If request T is made and request S is not made, the system moves to process 7. After execution of process 2, if zero (Z) status is 1, the system moves to process 3, and if it is 0, the system moves to process 5. Other movements are made unconditionally after execution of each process.
If the process flow is carried out by the conventional CPU, the interrupt process is needed to move from process 0 to process 1 or 7, and the branch instruction is needed to move from process 2 to process 3 or 5. Consequently, the overhead occurs on the point of interrupt or branch instruction for process switching, which may hinder the switching in real time, for example.